Initializing
Initializing
Pushing the boundaries of hardware-software co-design through rigorous experimentation, logic synthesis, and edge intelligence research.
Investigation into gate-level power reduction techniques for 32-bit arithmetic units using specialized carry-lookahead logic in Verilog.
Behavioral modeling → Synthesis → Power analysis using Xilinx Power Estimator (XPE).
Achieved 15% reduction in dynamic power consumption while maintaining sub-10ns propagation delay.
Analyzing the feasibility of running quantized TensorFlow Lite models for real-time agricultural anomaly detection.
Model training in Python → TOCO Quantization → C++ Inference on ESP32-S3.
Successful classification of 5 soil types with 92% accuracy and 120ms inference latency.
Continuous hardware simulation and model training...